1. Field of the Invention
The present invention relates to a flash memory device, and more particularly, to a flash memory device having an SONOS (Polysilicon-Oxide-Nitride-Oxide-Semiconductor) structure and a method for fabricating the same, and programming and erasing methods thereof, to improve reliability such as endurance and retention.
2. Discussion of the Related Art
A typical example of a nonvolatile memory device, in which data is not erased even though a voltage is not applied, is EEPROM (Electrically Erasable Programmable Read Only Memory). Generally, the EEPROM takes a scheme using a floating gate-type cell. With rapid development of high-integration device, it necessarily requires the decrease in a size of the floating gate-type cell according to the related art. However, it is impossible to decrease the cell size since it requires a high voltage on programming and erasing modes and it is difficult to obtain the margin of process for defining tunneling. In this reason, various nonvolatile memory devices such as SONOS, FeRAM, SET and NROM have been studied actively as the substitute for the floating gate-type cell. Among them, SONOS cell has attracted great attentions as the next nonvolatile memory device, which can substitute for the stacked floating gate-type cell.
Hereinafter, a related art SONOS-type flash memory device will be described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view illustrating a unit cell of a related art SONOS-type flash memory device.
As shown in FIG. 1, the SONOS-type flash memory device according to the related art includes a p-type semiconductor substrate 11, an ONO layer 18, a control gate 15, and source and drain regions 16 and 17. At this time, the ONO layer 18 is formed in a method of sequentially stacking a first oxide layer 12, a nitride layer 13 and a second oxide layer 14. Then, the control gate 15 is formed on the ONO layer 18, and the source and drain regions 16 and 17 are formed in a method of implanting highly doped n-type impurity ions into the surface of the semiconductor substrate 11 at both sides of the control gate 15. At this time, the first oxide layer 12 acts as a tunneling oxide layer, and the nitride layer 13 acts as a memory layer by controlling a threshold voltage Vth by charging electric charge to a trap site or discharging the electric charge. Also, the second oxide layer 14 acts as a blocking oxide layer preventing loss of the electric charge.
In the aforementioned SONOS-type flash memory device according to the related art, a programming operation uses a CHEI (Channel Hot Electron Injection) method, and an erasing operation uses an HHI (Hot Hole Injection) method to remove injected electrons.
On the programming operation, a predetermined positive (+) voltage is applied to the drain region 17 and the control gate 15, and the source region 16 and the semiconductor substrate (body) are ground. Under this condition, according as a bias is applied, channel electrons are accelerated by a lateral electric field formed from the source region 16 to the drain region 17, whereby the channel electrons become hot electrons around the drain region 17. Also, the hot electrons jump over a potential barrier of the first oxide layer 12, and are locally trapped to a trap level of the nitride layer 13 around the drain region 17, thereby increasing the threshold voltage. This programming method is referred to as CHEI (Channel Hot Electron Injection).
On the erasing operation, a predetermined positive (+) voltage is applied to the drain region 17, and a predetermined negative (−) voltage is applied to the control gate 15. Also, the source region 16 and the semiconductor substrate (body) 11 are ground. Under this condition, according as a bias is applied, a depletion region is formed in the n-type drain region 17 by a high electric field formed in an overlap area between the drain region 17 and the control gate 15. In the depletion region, pairs of electron and hole are generated by band to band tunneling. Then, the electron escapes to the n-type region, and the hole is accelerated by a lateral electric field of the depletion region, whereby the hole is changed to a hot hole. The hot hole jumps over an energy barrier between the first oxide layer 12 and the semiconductor substrate 11, injected and trapped to a valance band of the nitride layer 13, thereby performing the erasing operation lowing the threshold voltage. This erasing method is referred to as HHI (Hot Hole Injection).
Also, the aforementioned SONOS-type flash memory device records 2-bit data in one cell. That is, the programming operation of the related art SONOS-type flash memory device uses the CHEI (Channel Hot Electron Injection) method, and the erasing operation thereof uses the HHI (Hot Hole Injection) method. By applying the voltage of the aforementioned condition, the electron is trapped to the nitride layer 13 around the drain region 17, thereby storing 1-bit data. Then, a predetermined positive (+) voltage is applied to the source region 16 and the control gate 15, and the drain region 17 and the semiconductor substrate (body) are ground, whereby hot electrons are generated around the source region 16. The hot electrons jump over the potential barrier of the first oxide layer 12, and are trapped to the nitride layer 13 around the source region 16, thereby storing 1-bit data.
In the programming and erasing operations, if the electron and hole are shallowly trapped to the nitride layer 13, program and erase cycling becomes low. Accordingly, the technology for overcoming this problem has been published in IEDM document (Novel Operation Schemes to Improve Device Reliability in a Localized Trapping Storage SONOS-Type Flash Memory, 2003).
On the programming operation, when the hot electrons jump over the potential barrier of the first oxide layer 12, and are trapped to the nitride layer 13 around the drain region 17, some of the hot electrons are deeply trapped to the nitride layer 13, and the other hot electrons are shallowly trapped to the nitride layer 13. Among them, the hot electrons shallowly trapped to the nitride layer 13 escape during a storage period due to a damage of the first oxide layer generated by the program and erase cycling, thereby generating loss of the electric charge.
According to IEDM document published in 2003, it is proposed to carry out an electrical anneal after Hot Electron Injection of the programming operation or after Hot Hole Injection of the erasing operation, to improve over-erase in state of the low threshold voltage, and to prevent loss of the electric charge in state of the high threshold voltage. On the erasing operation, after hole injection, the electron and hole are recombined in the erasing electrical anneal. On the programming operation, after electron injection, the electron shallowly trapped to the nitride layer is removed, and the electron deeply trapped to the nitride layer remains by the programming electrical anneal. In the erasing electrical anneal, as shown in FIG. 1, the source region 16 and the drain region 17 are ground, and the pulse (10 ms) of 10V is applied to the control gate 15. In the programming electrical anneal, the source region 16 and the drain region 17 are ground (0V), and the pulse (10 ms) of −4V is applied to the control gate 15.
However, the aforementioned IEDM document has the following problems.
On the programming operation, the electrons shallowly trapped to the nitride layer are removed by the programming electrical anneal, thereby decreasing loss of the electric charge. After programming, it is impossible to remove the hopping electrons moved (spread) to a lateral side by the programming electrical anneal. Accordingly, even in case of Hot Hole Injection in a large amount on the erasing operation, the trapped electrons are not removed completely, thereby degrading reliability. Especially, when separately programming data to the nitride layer around the source region and the drain region, for example, programming 2-bit data in one cell, the aforementioned problem becomes more serious.